Your home nano HyperScaler

Nu1 is a Foundation project with the objective of building a high-performance RISC-V HyperScaler infrastructure, based on the following criteria:

Robustness and fault tolerance
Low energy consumption
High availability
Scalability
OpenSource
Development is carried out with the LYME software stack (Linux Ubuntu, Cowbo(y), Mnesia, Erlang) embedded on VisionFive2 (RISC-V 64bit, 4Core, 8GB, Superior Performance {Frequence：2GHz@TSMC 12nm | SPECint2006：9.4/GHz}).

Using a relatively simple and uniform set of reduced instructions, called RISC (Reduced Instruction Set Computer), notably ARM; PowerPC; Raspberry PI; Samsung, allows coding (execution of a minimum number of types of computer instructions) in such a way as to operate at higher speed and to perform more MIPS (millions of instructions per second) since each instruction performs a specific and low complexity task.

Performance: Instructions are executed in a single clock cycle, allowing for fast and efficient performance.

Complexity: Simpler instructions require more work from the compiler to optimize program performance.

Efficient Pipeline: Simplicity of instructions allows for very efficient execution pipelines, which improves performance

Optimized for Embedded Systems: RISC processors are often used in embedded systems (smartphones, tablets, etc.) due to their low power consumption and reduced cost.

Compared to Intel and AMD x86-64 which offers a complex and rich instruction set. Some instructions can perform complex operations in a single step.

Performance: Able to execute complex instructions directly, which can be more efficient for some applications.

Complexity: Complex instructions can require multiple clock cycles, but hardware can optimize execution.

Backward Compatibility: The x86-64 architecture is the result of many years of evolution, resulting in a very rich instruction set that is compatible with older generations of processors.

Comparison table